1. Technical Field
Embodiments of the invention relate to a method for use in semiconductor fabrication and a related apparatus adapted for use in semiconductor fabrication. In particular, embodiments of the invention relate to an overlay measuring method and a semiconductor fabrication equipment management system adapted to perform the overlay measuring method.
This application claims priority to Korean Patent Application No. 10-2006-0060482, filed Jun. 30, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Discussion of Related Art
Recently, the rapid spread of information technology such as computers has generated a demand for the development of new semiconductor devices having relatively high operation speeds and relatively high storage capacities. Accordingly, semiconductor devices having relatively high degrees of integration, relatively high levels of reliability, and relatively high operation speeds have been developed.
In the semiconductor industry, unit processes used in the fabrication of semiconductor devices are being developed with the goal of ensuring high yield rate and throughput for each of the unit processes, and research is being conducted on methods and apparatuses for detecting (i.e., measuring) process errors in individual unit processes. In particular, photolithography processes, which are essential to the fabrication of a semiconductor device, require compensation for frequent variations in process conditions and apparatuses for making those compensations.
One substantial problem for photolithography processes is the misalignment of photoresist patterns formed through exposure and development. In addition, accurate alignment becomes increasingly difficult as wafer size increases, the number of photolithography processes performed increases, and alignment margins decrease due to increasing demand for semiconductor devices having higher integration densities. In order to prevent the misalignment of photoresist patterns, an overlay measuring process needs to be optimized to check the alignment conditions of photoresist patterns already formed on a wafer.
U.S. Pat. Nos. 5,696,835 and 6,357,131 disclose methods for performing an optimized overlay measuring process.
A conventional overlay measuring method will now be described. In a conventional overlay measuring method, a reference recipe that includes information concerning chip pattern images formed on a reticle in an exposure unit used in forming photoresist patterns on a wafer is required in order to make an overlay measurement of the wafer. A host computer that controls an apparatus computer in an overlay measuring apparatus outputs the reference recipe. The overlay measuring apparatus uses the reference recipe output from the host computer to set a map that corresponds to a plurality of chip patterns formed on the wafer. The number of the chip patterns may depend on the size of the wafer or the size of the chip patterns formed on the wafer. For example, about 77 (5×), 44, or 17 (25×) chip patterns may be formed on an 8-inch wafer.
When an overlay measuring process comprising a preliminary overlay measuring process and an overlay evaluation process is performed on the wafer on which the chip patterns are formed, the apparatus computer needs to set a map using a reference recipe having images that correspond to the chip patterns. If an incorrect reference recipe is input to the apparatus computer by mistake, the apparatus computer will set a map based on the incorrect reference recipe and perform an overlay measuring process using (i.e., based on) the map, which may result in overlay measurement errors in the overlay evaluation process (i.e., may generate erroneous results).
An overlay mark on which an overlay evaluation process (i.e., a substantive overlay measuring process) is performed represents a correlation between thin films that have been formed on the wafer. Since there are various kinds of overlay marks, it is not possible to provide position information for a specific overlay mark when setting up the map. Accordingly, the overlay evaluation process is performed on the overlay mark after an operator manually selects and records position information corresponding to the overlay mark. However, the operator may input incorrect position information for the overlay mark to the apparatus computer, which may cause overlay measurement errors (i.e., produce erroneous results) in the overlay evaluation process.
The apparatus computer uses an optical unit of the overlay measuring apparatus to measure the relative positions of (i.e., an overlapped position between) an upper photoresist pattern formed on the wafer (which may be referred to hereinafter as a “son ruler”) and a lower photoresist pattern (which may be referred to hereinafter as a “mother ruler”) that is disposed at least one layer below the upper photoresist pattern. It is difficult to make an overlay measurement (i.e., evaluation) of the layer patterns formed in individual chip areas of the wafer because the layer patterns are very complex. Accordingly, the overlay evaluation process may be performed using a scribe line formed on a portion of the wafer disposed outside of the chip area of the wafer and an additional overlay mark formed at the center of the chip area.
In more detail, the overlay measuring process is performed according to a predetermined ratio according to the number of shots which are provided on a single wafer, or the size of the wafer. In addition, the overlay evaluation process is performed on the entire wafer by sequentially performing the overlay evaluation process on various portions of the wafer using the optical unit of the overlay measuring apparatus. The apparatus computer that controls the overlay measuring apparatus enables the optical unit to set alignment marks as reference points and to measure (i.e., evaluate) the overlay mark at increasing magnifications.
When a wafer is provided to the overlay measuring apparatus after photolithography has been performed on the wafer, the apparatus computer controls the overlay measuring apparatus such that the overlay measuring apparatus recognizes a central position of the wafer and a lens of the optical unit magnifies the central position of the wafer to measure an overlay mark on the wafer. The optical unit is controlled to magnify a pattern with a size of about 12 mm (12K) and to acquire an image of the pattern.
The lens of the optical unit is controlled to find and magnify a wafer alignment mark that has the shape of a cross (“+”), is separated from the center of the wafer by a predetermined distance, and is formed on a boundary of a plurality of chip areas. As an example, the central position of the alignment mark may be set as a shot reference point and can be measured at a magnification where an image of a pattern having a size of about 750 μm is acquired by the lens of the optical unit. At this time, the optical unit finds the alignment mark (i.e., the shot reference point) disposed proximate the center of the wafer in accordance with a control signal output by the apparatus computer and based on the map, and then magnifies and projects the surface of the wafer. At this time, the alignment mark (i.e., shot reference point) may be set such that it is a reference point having coordinates (0, 0) and is disposed at a lower-left (LL) portion of one of the chip areas.
The lens of the optical unit is controlled to magnify and project an overlay mark that is separated from the central position of the alignment mark by a predetermined distance. The overlay mark includes a mother ruler, a son ruler, and a label. The mother ruler is formed on a lower pattern layer that is patterned on the wafer by a first semiconductor fabrication process. The son ruler is formed above the mother ruler by a second semiconductor fabrication process after the first semiconductor fabrication process, and is formed such that it overlaps with the mother ruler and is separated from the mother ruler by a predetermined distance in a direction that is substantially perpendicular with the working surface of the wafer. The label is formed in the same layer as either the mother ruler or the son ruler and comprises a name that identifies during which semiconductor fabrication processes the mother and son rulers were formed, respectively. The label may include information about various layers formed sequentially on the wafer. For example, a label “40 TO 10” indicates an overlay mark that is measured to calculate an overlay compensation value between the fourth layer formed on the wafer and the first layer formed on the wafer.
A plurality of overlay marks, each having a specific identification name (i.e., label), are formed adjacent to the center and adjacent to corners of the chip area, respectively. Accordingly, at an early stage of the overlay measuring process (i.e., during the preliminary overlay measuring process), an operator selects overlay marks and inputs measurement data for the selected overlay marks, each of which is separated from the alignment mark (i.e., shot reference point). The measurement data is provided to the apparatus computer so that the apparatus computer can perform the subsequent overlay evaluation process in accordance with the measurement data received at the early stage of the overlay measuring process (i.e., during the preliminary overlay measuring process).
Thus, in accordance with the conventional overlay measuring method, when incorrect measurement data corresponding to a position of an overlay mark is input to the apparatus computer by an operator during the preliminary overlay measuring process, erroneous results may be returned (i.e., overlay measurement errors may occur), which may result in accidents on semiconductor production lines.